ICACT20260254 Question.1
Questioner: hhl9438@chungbuk.ac.kr 2026-02-09 오후 12:46:34 |
ICACT20260254 Answer.1
Answer by Auhor qga0809@chungbuk.ac.kr 2026-02-09 오후 12:46:34
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| Currently, you use 7 input features. If you add dynamic data like real-time traffic or weather, how much would it impact the hardware resource usage and latency? |
Thank you for the question. Adding traffic or weather features would mainly affect the first hidden layer. Expanding from 7 to 10-12 features would increase first layer parameters by 40-70%, but overall resource increase would be around 10-15%. Due to our pipelined architecture, latency impact would be minimal, less than 5%. The current 0.005454ms inference time would still meet sub-millisecond requirements. As mentioned in our future work, we plan to incorporate these features with quantization and pruning techniques to maintain efficiency. |
ICACT20260254 Question.2
Questioner: mrajhans@paloaltonetworks.com 2026-02-11 오전 9:13:10 |
ICACT20260254 Answer.2
Answer by Auhor qga0809@chungbuk.ac.kr 2026-02-11 오전 9:13:10
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| How does the proposed MLP-based accelerator compare to LSTM-based approaches in terms of prediction accuracy and robustness, and what is the quantitative trade-off between the achieved latency gains and any loss in modeling temporal dependencies? |
Thank you for the question. Our current work focuses on demonstrating FPGA hardware acceleration feasibility rather than a comprehensive accuracy benchmark against LSTM. The key design rationale is that our destination prediction task is a contextual feature-based classification where temporal patterns are explicitly encoded as input features, making recurrent structures unnecessary. The 99.1% prediction confidence and 68.53× speedup over ARM software validate this approach, and we plan to provide a detailed accuracy comparison in future work. Thank you. |
ICACT20260254 Question.3
Questioner: Lee19711936516@163.com 2026-02-11 오후 3:32:26 |
ICACT20260254 Answer.3
Answer by Auhor qga0809@chungbuk.ac.kr 2026-02-11 오후 3:32:26
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| The FPGA-based MLP hardware accelerator designed in this paper adopts a four-layer feedforward architecture, with seven input features and six destination categories as output. The number of neurons in the hidden layers decreases pyramidally. What are the core considerations behind this neuron configuration design? Why were ReLU and Softmax chosen as the activation functions for the hidden and output layers, respectively? |
Thank you. The pyramidal configuration expands from 7 inputs to 64 neurons to capture diverse feature interactions, then progressively compresses to 32 and 16 to extract higher-level patterns while reducing multiply-accumulate operations, DSP slices, and BRAM usage on the Zynq-7000 platform. ReLU was chosen for hidden layers because it requires only a simple max(0, x) comparison—no exponential or division—enabling minimal resource usage and predictable pipeline timing on FPGA, unlike sigmoid or tanh. Softmax was selected for the output layer because the six destination classes are mutually exclusive, and it produces a normalized probability distribution enabling confidence-based decision making. Thank you. |
ICACT20260254 Question.4
Questioner: Lee19711936516@163.com 2026-02-11 오후 3:37:30 |
ICACT20260254 Answer.4
Answer by Auhor qga0809@chungbuk.ac.kr 2026-02-11 오후 3:37:30
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| The paper states that this MLP hardware accelerator achieves a 68.53× performance improvement compared to an ARM-based software implementation, with an inference time of only 0.005454ms. On the Zynq-7000 SoC platform, what specific hardware optimization techniques (such as interface design, architecture design, etc.) did the researchers employ to achieve this low-latency inference performance? |
Thank you. The 68.53× speedup fundamentally comes from the difference between sequential software execution on the ARM Cortex-A9 and parallel hardware execution on the dedicated PL accelerator, combined with the AXI Stream interface that enables direct PS-PL data streaming without DDR memory bottlenecks. The MLPs feed-forward structure further enables efficient hardware pipelining without recurrent data dependencies. We acknowledge that specific HLS optimization details and resource utilization analysis were not fully elaborated in this paper due to page constraints, and plan to include them in our extended work. Thank you. |
