ICACT20260320 Question.1
Questioner: wangsy@dsp.ac.cn 2026-02-06 오후 5:25:08 |
ICACT20260320 Answer.1
Answer by Auhor zhaozx@dsp.ac.cn 2026-02-06 오후 5:25:08
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| How does the refill path of GCCache ensure that each piece of data corresponds exactly to each request? Does it require reordering of the buffer (reorder buffer) or tag matching? |
GCCache receives requests from multiple pipelines, each of which is assigned a binary code and corresponds to a fixed Pipeline ID (note: not PID). This Pipeline ID accompanies the entire request processing flow: during the clock cycle for determining whether a request hits the cache, the Pipeline ID is temporarily stored in the Status RAM of the Cache Subsystem. If a request hits the cache, the Cache Subsystem will feed back the Pipeline ID together with the hit result to the Scheduler Subsystem, and its Response Handler module will accurately return the result to the corresponding pipeline based on the Pipeline ID. If a request misses the cache, the Pipeline ID will be stored in the Outstanding Table of the ORP Subsystem; after the host returns the context information, the ORP Subsystem will synchronize the Pipeline ID and context information to the Scheduler Subsystem. Given the small number of pipelines in the peripheral network card, the Pipeline ID occupies a limited number of bits and incurs extremely low RAM resource overhead, so we adopt the design scheme of in-path caching.
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ICACT20260320 Question.2
Questioner: wangsy@dsp.ac.cn 2026-02-06 오후 7:24:25 |
ICACT20260320 Answer.2
Answer by Auhor zhaozx@dsp.ac.cn 2026-02-06 오후 7:24:25
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| When "the same context/ the same address" undergoes update or becomes invalid during the retrieval process (such as QP status change, MPT/MTT update), how does GCCache ensure that the multiple outstanding misses after merging will not read outdated/inconsistent contexts? |
This problem cannot be solved by GCCache alone and needs to be explained from the perspective of the network card. First, a core premise must be clarified: there is an essential difference between the cache model of traditional computer architecture and that of RNIC, which is also one of the key challenges to be addressed in the development of RDMA network cards. The traditional cache model follows a hierarchical structure of CPU—Cache—Main Memory, where all data queries and modifications by the CPU are processed through the cache, thus the cache coherence problem can be properly resolved. In the cache model of RDMA network cards, however, in addition to the network cards direct access to the main memory (following the Pipeline—GCCache—Host Memory path), the host driver can also directly read and write the main memory. What is more, the network card has no perception of the main memory modifications made by the host driver. In this case, if stale data remains in the cache, it will easily cause abnormal operation of the network card, which greatly increases the difficulty of solving the cache coherence problem in this scenario. To address this issue, our solution is as follows: before the host driver modifies the main memory data (mainly various context information), it must first send a notification to the network card through a dedicated register; upon detecting the notification, the network card will initiate a clear request with the opcode of Clear to GCCache. If the request hits the cache, GCCache will immediately execute the cache clearing operation to ensure no stale data remains in the cache, thereby guaranteeing that the context information obtained by GCCache from the host is always the latest. |
ICACT20260320 Question.3
Questioner: zhaoyb@dsp.ac.cn 2026-02-09 오후 4:16:02 |
ICACT20260320 Answer.3
Answer by Auhor zhaozx@dsp.ac.cn 2026-02-09 오후 4:16:02
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| The paper mentions that GCCache is also applicable to 400 Gbps applications. As the bandwidth doubles, the requirements for clock frequency or parallel pipeline width become more stringent. At these higher rates, can the current settings still achieve timing convergence? Would it require additional clock cycles? |
A 400Gbps RNIC typically uses a frequency of 500Hhz and a bus bit width of 1024 bits. If 1024B packets are processed at line speed, the cache needs to return data within 8 clock cycles (in the case of a cache hit). In theory, our cache can still meet the processing requirements of a 400G RNIC. Our team is currently developing a 400G RNIC. |
ICACT20260320 Question.4
Questioner: zhaoyb@dsp.ac.cn 2026-02-09 오후 4:19:43 |
ICACT20260320 Answer.4
Answer by Auhor zhaozx@dsp.ac.cn 2026-02-09 오후 4:19:43
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| The ORP subsystem relies on the PID pool and the Outstanding Table to track requests. In scenarios of extreme congestion or massive cache misses, if the PID pool is exhausted or the table becomes full, what should the system do to keep balanced? |
The capacity of the PID pool depends on the performance requirements of the network card in case of cache misses. Our PID pool capacity is 64, which means that when the PCIE delay is 1us, theoretically GCCache can meet a throughput of 64Mpps in extreme cases, which is much greater than the data processing capacity of our current peripheral network cards. |
