ICACT20260323 Question.1
Questioner: tanghr@dsp.ac.cn 2026-02-06 오전 6:48:41 |
ICACT20260323 Answer.1
Answer by Auhor wangsy@dsp.ac.cn 2026-02-06 오전 6:48:41
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| How does the circular buffer in HPPC manage cyclic overwrites without losing packets that might be needed for retransmission, and how does it maintain sequential writes to avoid fragmentation? |
HPPC employs a two-layer protection mechanism to avoid the issue of "retransmission due to coverage failure": The ring buffer capacity is allocated according to Cring ≥ α⋅R⋅Tseg, which is set to cover a time window of "detection → NACK response → read back → retransmission" once, ensuring that the packet is still present before the write pointer wraps around. At the same time, the index includes epoch/valid bits, so even if it is overwritten, it will be deemed invalid and no incorrect packet will be read.
Sequential writing without fragmentation relying on the structure itself: There is only one global write pointer that continuously appends writes to DDR_data (fixed slot, aligned according to DDR burst), without performing stream allocation or linked list scattered writes. Therefore, it is naturally a continuous burst write. |
ICACT20260323 Question.10
Questioner: k_ylin1125@163.com 2026-02-10 오후 11:58:39 |
ICACT20260323 Answer.10
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 11:58:39
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| What exactly is your core contribution? How does it differ from the existing P4 / SmartNIC solutions? |
HPPC’s core contribution is a DRAM-friendly packet cache for hop-local recovery on high-BDP WAN-like segments. Unlike P4/Switch designs that are constrained by on-chip SRAM and pipeline resources, HPPC assumes an in-path node with abundant off-chip DDR and organizes both data and metadata so that cache operations become mostly sequential DDR bursts. Compared with NIC-only recovery, HPPC shortens the loss-repair loop to roughly one segment RTT while keeping endpoints unchanged. |
ICACT20260323 Question.11
Questioner: 13060061882@163.com 2026-02-11 오전 12:06:11 |
ICACT20260323 Answer.11
Answer by Auhor wangsy@dsp.ac.cn 2026-02-11 오전 12:06:11
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| Where are the HPPC devices deployed? Do the remote hosts need to be modified? |
Deployed at two in-path gateways/nodes forming a reliability segment; no changes are required to end-host TCP/RDMA. |
ICACT20260323 Question.2
Questioner: k_ylin1125@163.com 2026-02-06 오전 6:44:15 |
ICACT20260323 Answer.2
Answer by Auhor wangsy@dsp.ac.cn 2026-02-06 오전 6:44:15
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| Why is hop-local necessary? Can end-to-end retransmission work instead? |
On high-BDP paths, end-to-end recovery pays at least one end-to-end RTT per loss, which inflates the recovery time and disrupts the sender’s congestion window dynamics. Hop-local recovery confines repair within the WAN segment, so the loss is detected and repaired within one segment RTT, reducing the effective penalty per loss and maintaining higher goodput without modifying TCP/RDMA endpoints. |
ICACT20260323 Question.3
Questioner: qga0809@chungbuk.ac.kr 2026-02-10 오후 4:57:52 |
ICACT20260323 Answer.3
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 4:57:52
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| Your prototype achieves over 95 Gb/s goodput at 1% loss rate for large packets. However, you mentioned that small packets below 1024B hit FPGA packet-rate processing limits. What architectural modifications would be needed to achieve line-rate performance for small packets as well? |
Small packets are limited by the FPGA packets-per-second (pps) pipeline, not the cache idea. To reach line rate we need:Increase internal datapath width or parallelism (wider AXI-stream or multi-lane pipelines);Use write-combining/batching for DDR payload writes and index updates to cut per-packet DDR transactions;Keep more hot metadata (L1, active-flow state) on-chip (BRAM/URAM caches) to reduce random-access overhead. |
ICACT20260323 Question.4
Questioner: hejf@dsp.ac.cn 2026-02-10 오후 4:59:33 |
ICACT20260323 Answer.4
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 4:59:33
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| How does HPPC leverage DDR optimization to improve packet cache throughput and latency on WAN nodes? |
HPPC “DDR-optimizes” the cache by turning random accesses into sequential burst traffic:
Unified DDR ring buffer for payloads: one global write pointer streams packets sequentially, avoiding per-flow allocation, fragmentation, and scattered DRAM writes.
Compact two-level index on a separate DDR channel: maps (flow, seq) to ring locations in O(1) with bounded metadata accesses, reducing contention with payload DDR. |
ICACT20260323 Question.5
Questioner: hejf@dsp.ac.cn 2026-02-10 오후 5:03:23 |
ICACT20260323 Answer.5
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 5:03:23
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| What is the main bottleneck in conventional WAN packet caching that HPPC targets, and how does HPPC’s design mitigate it? |
Main bottleneck: Conventional WAN packet caches rely on per-flow buffers/linked lists plus fine-grained indexing, which triggers pointer chasing and scattered DRAM accesses (short bursts, poor row-buffer locality, high read amplification) and quickly becomes DRAM-efficiency limited at line rate; per-packet indexing also doesn’t scale with limited on-chip SRAM.
HPPC mitigation: HPPC uses a unified DDR ring to enforce sequential burst writes, a compact two-level flow-aware index (placed in DDR_idx) for O(1) (flow, seq) lookups, and range-based NACK coalescing to turn repair reads into long aligned bursts—reducing randomness and amplification to sustain high throughput with low repair latency. |
ICACT20260323 Question.6
Questioner: zhaozx@dsp.ac.cn 2026-02-10 오후 4:54:26 |
ICACT20260323 Answer.6
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 4:54:26
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| How do you ensure that you wont read overwritten data? What is the actual function of epoch/validity check? |
Because the DDR_data ring overwrites old slots, an index entry may become stale. HPPC uses epoch bits/tags to bind an address entry to a particular ring “generation.” When a slot is overwritten, the epoch changes; during readback, HPPC checks the epoch to ensure the entry still matches the current generation. This prevents retransmitting incorrect payloads due to overwritten/evicted entries. |
ICACT20260323 Question.7
Questioner: zhaozx@dsp.ac.cn 2026-02-10 오후 4:55:20 |
ICACT20260323 Answer.7
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 4:55:20
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| Why did you use "unified ring DDR_data + two-level DDR_idx"? What was the most crucial design motivation? |
The unified DDR_data ring enables sequential writes for all cloned packets, which matches DRAM’s strength. The two-level DDR_idx avoids per-packet random metadata in large flat tables and avoids pointer chasing in linked lists. Together, they reduce random DRAM accesses, improve row-buffer locality, and keep repair readbacks as long coalesced bursts, which is essential for 100Gb/s. |
ICACT20260323 Question.8
Questioner: 13060061882@163.com 2026-02-11 오전 12:07:05 |
ICACT20260323 Answer.8
Answer by Auhor wangsy@dsp.ac.cn 2026-02-11 오전 12:07:05
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| How do downstream nodes detect packet loss? |
The downstream tracks per-flow sequence continuity and sends NACK(flow, seq/range) upon detecting gaps. |
ICACT20260323 Question.9
Questioner: 13060061882@163.com 2026-02-10 오후 11:57:11 |
ICACT20260323 Answer.9
Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 11:57:11
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| Why is the "small packet throughput platform" attributed to the packet rate bottleneck in the result page, rather than DDR or cache miss? |
At small packet sizes, achieving the same line-rate Gb/s requires much higher packets-per-second. If goodput plateaus primarily when packet size decreases (even at low loss) and the normalized curves for large packets overlap, it suggests the dominant constraint is per-packet processing (parser, bookkeeping, enqueue/dequeue, NACK handling) rather than DRAM bandwidth or cache misses. In other words, the system hits a PPS ceiling rather than a DDR_data/DDR_idx contention limit. |
