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IEEE/ICACT20260323 Slide.01        [Big Slide]       [YouTube]	Oral Presentation
	Hello, I¡¯m Shuangyan Wang from the Intelligent Networking and Information Processing Lab, Institute of Acoustics, CAS. This talk presents HPPC, a DDR-optimized packet caching architecture for hop-local loss recovery on high-speed, long-RTT WAN segments. HPPC places a memory-rich in-path node that buffers recent packets in a unified DDR ring and uses a compact two-level flow-aware index for O(1) lookup. When the downstream node detects sequence gaps, it issues NACKs and the upstream node performs fast readback and retransmission within one segment RTT, without requiring changes to TCP/RDMA endpoints.

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