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IEEE/ICACT20260323 Slide.03
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Pure end-to-end recovery is inherently limited by the full RTT, which becomes costly on WANs. Even NIC-based selective retransmission still pays full-path feedback delay, and it requires significant per-flow state that must fit into limited on-chip SRAM. As the number of flows and the effective window size grow with BDP, SRAM becomes the scaling bottleneck. This motivates an in-path approach that can leverage larger off-chip memory while keeping the critical operations fast. | |
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