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There are several challenges in implementing Fully-Connected Layers (FCL) when implementing SNNs. Firstly, FCL requires a substantial number of wires, leading to increased complexity, expanded area, longer wire delays, and reduced scalability when implemented on a chip. A second challenge arises from the manual implementation required for SNNs, especially in low-power scenarios that require asynchronous or analog circuit design. This manual design process requires significant time and effort to implement wire-intensive FCLs in SNNs.
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