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As the demand for high-speed data transmission continues to grow, optimizing flow rule processing becomes critical to maintaining network efficiency. Traditional CPU-based solutions face scalability and performance challenges when processing large numbers of flow rules in real-time. As a solution, we propose the use of FPGA (Field-Programmable Gate Array) technology to accelerate this process and significantly improve overall system performance. While DPDK provides an efficient framework for high-speed packet processing, there is a notable gap in FPGA architecture support for offloading flow rule processing using the rte_flow API. FPGA architecture as well as hardware and software communication interfaces will be presented in the following slides |
IEEE/ICACT20250056 Slide.06
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