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The second challenge is Redundant Host Accesses. In real workloads, consecutive requests received by the cache may actually be identical. For example, multiple packets from the same memory region may arrive in a short burst. As shown in figure a, if the first request from MR1 misses the cache, it triggers a fetch from the host memory. But before the response comes back, several more MR1 requests may arrive. In current designs, each of these requests will also trigger a separate host access, even though theyre all asking for the same context. This results in significant PCIe bandwidth waste, as highlighted in red here. What we want is shown in figure b: when repeated requests miss the cache, they should only trigger one host access, and all of them should share the same response. |
IEEE/ICACT20260320 Slide.06
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