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IEEE/ICACT20260254 Slide.07        [Big Slide]       [YouTube]	Oral Presentation
	Several studies explored LSTM acceleration on FPGA, including Han et al.s ESE and Zhang et al.s pipeline optimization work. However, LSTM has fundamental hardware limitations. The 3 gate architecture requires complex control logic, and sequential dependencies limit parallelization. In contrast, MLPs feed forward structure enables straightforward parallelization, achieving higher throughput and lower latency with fewer hardware resources.

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