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Here we summarize the design targets and the key constraints. We want line-rate caching and loss repair at 100 Gb/s, fast enough to fetch missing packets quickly after NACKs arrive, and scalable to thousands of concurrent flows under large BDP and non-zero loss. The constraints are mainly memory-related: on-chip SRAM cannot store a full per-packet index for multi-GB DDR, while DDR provides capacity but performs poorly under fine-grained random accesses. Therefore, the cache must avoid per-flow linked structures and align operations with DDRĄŻs burst-friendly behavior. |
IEEE/ICACT20260323 Slide.07
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