 |
In this slide, I present the hardware architecture implemented on the Xilinx Alveo U200. The packet enters the RX path and first passes through the Ingress Adapter, where its length is calculated and validity is checked. Metadata, including this information, accompanies the packet during processing. The Header Parser extracts necessary header fields from OSI layers 2, 3, and 4, ensuring compatibility with rte_flow API patterns. The Trans TCAM Rx module consolidates the extracted fields into a key, which is used to query Rule Tables for the appropriate actions. This same process is applied to the TX path during transmission. The Trans TCAM and Rule Table modules play a crucial role in flow rule processing. In the next slide, I will explain the operation of the Trans TCAM. |
IEEE/ICACT20250056 Slide.08
[Big Slide]