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IEEE/ICACT20260302 Slide.08        [Big Slide]       [YouTube]	Oral Presentation
	A key component of our design is the Per-Interface Cache System. At each interface, the cache is divided into K Sub-caches, organized by delay-difference levels. MIs are assigned to the sub-cache that best matches the delay of their potential detour path. At the output, we use a Weighted Round-Robin scheduler to ensure fair bandwidth allocation among these sub-caches.

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