 |
In one sentence, HPPC is a DDR-resident packet cache that converts caching into predominantly sequential DDR bursts using a unified ring plus a compact two-level index. Our contributions are: a flow-agnostic DDR ring for sequential writes without per-flow allocation; a two-level flow-aware index enabling O(1) mapping from (flow, seq) to ring location with small SRAM footprint; range-aware repair that coalesces NACKs into long burst readbacks to keep read amplification low; and a dual-DDR4 FPGA prototype validated at 100 Gb/s with strong goodput under loss and 1,000+ flows. |
IEEE/ICACT20260323 Slide.08
[Big Slide]