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IEEE/ICACT20260323 Slide.09        [Big Slide]	Oral Presentation
	This slide provides the cache overview. HPPC stores all packet payloads in a unified ring buffer in DDR_data, using a fixed slot size aligned to burst transfers, which makes the write path naturally sequential. Metadata is placed in a separate DDR_idx channel, implementing a two-level index: L1 keeps per-flow window and pointers, and L2 stores fixed-size segments of address entries. On-chip SRAM only caches a small set of hot L1 entries and control FIFOs. The result is a sequential data path with bounded O(1) index operations and elastic cache sharing across flows under a global cap.

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