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The event-based approach to information propagation of SNNs allows for low power consumption, and as a result, SNNs are receiving industry attention and neuromorphic architecture hardware such as IBM TrueNorth and Intel Loihi are being developed to accommodate itself. This paper proposes a linear leakage method inspired by the method used by Y. Kuang [18] and others in the development of neuromorphic chips. During the operation of the neuromorphic chip PKUNC64C, the voltage leakage within each time step is represented by subtracting a fixed value to accommodate the low power consumption of SNN. Equation (4) represents the way the chip updates the voltage at the hardware level.
Where 𝑈_𝑗 [𝑡] denotes the membrane voltage of the time step 𝑡 in the layer 𝑗, 𝑥_𝑖 is the spike signal from the presynaptic of the layer 𝑖, 𝑤_𝑖𝑗 is the connection weight of layer 𝑖 and layer 𝑗, 𝑠_𝑖𝑗 is the synaptic connectivity between layer 𝑖 and layer 𝑗, and 𝜆_𝑗 is the leakage constant of the layer 𝑗. This method reduces the chip computing power and improves the computational robustness.
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IEEE/ICACT20230030 Slide.11
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