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The signal integrity analysis confirmed the insertion loss, input reflection coefficient, NEXT, and FEXT values. In order to confirm changes in the eye diagram according to various conditions, a comparison was made between when the channel loss was not reflected and when it was reflected.
In the future, more accurate results will be possible by applying the connector model, cable model, and IBIS model of the actual memory used.
In addition, in the case of a PCB with a high-speed transmission signal, the influence of the back drilling and via pad on the back of the PCB should be considered.
In this case, if the size of the PCB is considerably large, the analysis time may be prolonged if a 3D analysis tool is utilized.
In conclusion, signal integrity analysis can be used as a pre-verification tool to shorten the design time and prevent design errors in advance when designing the PCB layout.
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IEEE/ICACT20250085 Slide.13
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