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IEEE/ICACT20230043 Slide.14        [Big Slide]	Oral Presentation
	We realize parallel BFS algorithm on VCU128 development board by emplying HBM and memory access scheduling module. The Table III shows the resource consumption of HBM interconnect module on FPGA, The Table IV shows the effective bandwidth of HBM built in interconnect module, the effective bandwidth of HBM clos interconnect module and HBM Connect on FPGA. Compared HBM Connect, the effective bandwidth of the clos interconnect is lower, but it uses less resources and it has scalability, which could be expanded to use more HBMs easily due to the orthogonal link selection. The experimental results show that the effective bandwidth of the HBM clos interconnect is more than twice that of the HBM built in interconnect, which is in line with expectations.

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