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In this paper, we propose a scheduling memory access architecture based on clos interconnect network, and analyze the influence of HBM bulit in interconnect structure on bandwidth. A experiment is done to test its performance. The experimental results show that proposed scheme can be implemented and effectively reduce the influence of HBM internal interconnection on bandwidth. We believe the scheduling memory access architecture will be improved in the future, so that the bandwidth of HBM can be used more effectively in parallel algorithm calculation. |
IEEE/ICACT20230043 Slide.15
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