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IEEE/ICACT20260323 Slide.16        [Big Slide]	Oral Presentation
	We implement HPPC on an FPGA-based NIC prototype with two independent DDR4 channels. DDR_data is dedicated to the payload ring buffer, while DDR_idx stores the index metadata, including the L1/L2 structures and the global queues. This separation reduces contention between large sequential payload bursts and smaller metadata accesses. The datapath is fully pipelined, covering parsing, cloning into the ring, NACK handling, index lookup, readback scheduling, and retransmission, with rate limiting and backpressure to protect normal forwarding.

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