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The architecture supports 9 Rule Tables (8 for Rx and 1 for Tx) and 165,888 flow rules while using minimal resources. This efficiency enables the development of additional packet processing blocks or expansion for more flow rules. The system achieves a throughput of 75 Gbps for 64-byte packets, increasing to 100 Gbps per port for packets of 128 bytes or more. The insertion rate for flow rules is impressive: 203.32 million rules per second for exact rules and 18.6 million rules per second for wildcard rules. The Wildcard Rule Table uses memory to store rules, which requires writing to the entire table for each insertion. In contrast, the Exact Rule Table uses a hash function to store rules at specific addresses, leading to a higher insertion rate. |
IEEE/ICACT20250056 Slide.18
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