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This article presents a comprehensive architecture for processing DPDK flow rules in hardware offload applications, integrating both firmware and FPGA hardware. The architecture supports up to 8 Rx and 1 Tx rule tables per Ethernet port, with 2048 wildcard matches and 16,384 exact match entries per table. It achieves a maximum throughput of 100 Gbps, with a rule insertion rate of 204 million rules per second for exact matches and 18 million rules per second for wildcard matches, laying a solid foundation for offload hardware applications. Future optimizations will focus on expanding the number of tables and enhancing flow rule handling, addressing the growing needs of modern networks and complex hardware offload applications, ultimately improving the performance and efficiency of smart network devices. |
IEEE/ICACT20250056 Slide.19
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