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This slide reports HPPC goodput under random loss on a WAN-like 100-Gb/s segment. The prototype is implemented on the MA-X1 platform with an XCVU9P FPGA and dual DDR4 channels. Traffic is generated by an IXIA XM100GE4CXP tester, and a WAN emulator fixes the RTT to 100 ms. We sweep packet sizes from 256 to 4096 bytes and random loss rates up to 5%.
The key result is that HPPC sustains near line-rate goodput for packet sizes of 1500 bytes and above up to 0.1% loss. Even at 1% loss, goodput stays above 95 Gb/s for 2048B and 4096B packets, and around 95 Gb/s for 1500B. The normalized curves for ¡Ã1500B largely overlap, indicating that performance is dominated by the fraction of DDR readback bandwidth consumed by repairs, rather than increasing lookup cost—consistent with sequential ring accesses and range-coalesced burst readback.
For smaller packets (¡Â1024B), throughput plateaus due to the FPGA packet-rate processing limit, not due to cache inefficiency or DDR contention. |
IEEE/ICACT20260323 Slide.20
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