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To conclude, fast loss recovery on WANs fundamentally requires a line-rate sliding-window cache. DDR provides the necessary capacity, but only if the cache is organized to be burst-friendly. HPPC achieves this with a unified ring buffer and a compact two-level index, turning most operations into sequential DDR accesses. Our FPGA prototype demonstrates strong goodput under non-zero loss on a 100 GbE segment. Future work includes evaluation with real WAN traces, multi-segment deployments, and exploring SmartNIC/ASIC implementations and tighter integration with congestion control. Thank you, and I¡¯m happy to take questions. |
IEEE/ICACT20260323 Slide.22
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