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2026-10-20, Week 43
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Virual Oral Question and Answer
IEEE/ICACT20260323 Question.10
Questioner: k_ylin1125@163.com    2026-02-10 오후 11:58:39 		IEEE/ICACT20260323 Answer.10
Answer by Auhor wangsy@dsp.ac.cn   2026-02-10 오후 11:58:39
What exactly is your core contribution? How does it differ from the existing P4 / SmartNIC solutions? HPPC’s core contribution is a DRAM-friendly packet cache for hop-local recovery on high-BDP WAN-like segments. Unlike P4/Switch designs that are constrained by on-chip SRAM and pipeline resources, HPPC assumes an in-path node with abundant off-chip DDR and organizes both data and metadata so that cache operations become mostly sequential DDR bursts. Compared with NIC-only recovery, HPPC shortens the loss-repair loop to roughly one segment RTT while keeping endpoints unchanged.

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