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IEEE/ICACT20260254 Question.3 Questioner: Lee19711936516@163.com 2026-02-11 오후 3:32:26	IEEE/ICACT20260254 Answer.3 Answer by Auhor qga0809@chungbuk.ac.kr 2026-02-11 오후 3:32:26
The FPGA-based MLP hardware accelerator designed in this paper adopts a four-layer feedforward architecture, with seven input features and six destination categories as output. The number of neurons in the hidden layers decreases pyramidally. What are the core considerations behind this neuron configuration design? Why were ReLU and Softmax chosen as the activation functions for the hidden and output layers, respectively?	Thank you. The pyramidal configuration expands from 7 inputs to 64 neurons to capture diverse feature interactions, then progressively compresses to 32 and 16 to extract higher-level patterns while reducing multiply-accumulate operations, DSP slices, and BRAM usage on the Zynq-7000 platform. ReLU was chosen for hidden layers because it requires only a simple max(0, x) comparison—no exponential or division—enabling minimal resource usage and predictable pipeline timing on FPGA, unlike sigmoid or tanh. Softmax was selected for the output layer because the six destination classes are mutually exclusive, and it produces a normalized probability distribution enabling confidence-based decision making. Thank you.

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