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IEEE/ICACT20260323 Question.3 Questioner: qga0809@chungbuk.ac.kr 2026-02-10 오후 4:57:52	IEEE/ICACT20260323 Answer.3 Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 4:57:52
Your prototype achieves over 95 Gb/s goodput at 1% loss rate for large packets. However, you mentioned that small packets below 1024B hit FPGA packet-rate processing limits. What architectural modifications would be needed to achieve line-rate performance for small packets as well?	Small packets are limited by the FPGA packets-per-second (pps) pipeline, not the cache idea. To reach line rate we need:Increase internal datapath width or parallelism (wider AXI-stream or multi-lane pipelines);Use write-combining/batching for DDR payload writes and index updates to cut per-packet DDR transactions;Keep more hot metadata (L1, active-flow state) on-chip (BRAM/URAM caches) to reduce random-access overhead.

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