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IEEE/ICACT20260254 Question.4 Questioner: Lee19711936516@163.com 2026-02-11 오후 3:37:30	IEEE/ICACT20260254 Answer.4 Answer by Auhor qga0809@chungbuk.ac.kr 2026-02-11 오후 3:37:30
The paper states that this MLP hardware accelerator achieves a 68.53× performance improvement compared to an ARM-based software implementation, with an inference time of only 0.005454ms. On the Zynq-7000 SoC platform, what specific hardware optimization techniques (such as interface design, architecture design, etc.) did the researchers employ to achieve this low-latency inference performance?	Thank you. The 68.53× speedup fundamentally comes from the difference between sequential software execution on the ARM Cortex-A9 and parallel hardware execution on the dedicated PL accelerator, combined with the AXI Stream interface that enables direct PS-PL data streaming without DDR memory bottlenecks. The MLPs feed-forward structure further enables efficient hardware pipelining without recurrent data dependencies. We acknowledge that specific HLS optimization details and resource utilization analysis were not fully elaborated in this paper due to page constraints, and plan to include them in our extended work. Thank you.

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