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Virual Oral Question and Answer
IEEE/ICACT20260323 Question.5
Questioner: hejf@dsp.ac.cn    2026-02-10 오후 5:03:23 		IEEE/ICACT20260323 Answer.5
Answer by Auhor wangsy@dsp.ac.cn   2026-02-10 오후 5:03:23
What is the main bottleneck in conventional WAN packet caching that HPPC targets, and how does HPPC’s design mitigate it? Main bottleneck: Conventional WAN packet caches rely on per-flow buffers/linked lists plus fine-grained indexing, which triggers pointer chasing and scattered DRAM accesses (short bursts, poor row-buffer locality, high read amplification) and quickly becomes DRAM-efficiency limited at line rate; per-packet indexing also doesn’t scale with limited on-chip SRAM. HPPC mitigation: HPPC uses a unified DDR ring to enforce sequential burst writes, a compact two-level flow-aware index (placed in DDR_idx) for O(1) (flow, seq) lookups, and range-based NACK coalescing to turn repair reads into long aligned bursts—reducing randomness and amplification to sustain high throughput with low repair latency.

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