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IEEE/ICACT20260323 Question.9 Questioner: 13060061882@163.com 2026-02-10 오후 11:57:11	IEEE/ICACT20260323 Answer.9 Answer by Auhor wangsy@dsp.ac.cn 2026-02-10 오후 11:57:11
Why is the "small packet throughput platform" attributed to the packet rate bottleneck in the result page, rather than DDR or cache miss?	At small packet sizes, achieving the same line-rate Gb/s requires much higher packets-per-second. If goodput plateaus primarily when packet size decreases (even at low loss) and the normalized curves for large packets overlap, it suggests the dominant constraint is per-packet processing (parser, bookkeeping, enqueue/dequeue, NACK handling) rather than DRAM bandwidth or cache misses. In other words, the system hits a PPS ceiling rather than a DDR_data/DDR_idx contention limit.

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