 ICACT20260254 Slide.01
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Hello everyone. I am Hyeon Muk Park from Chungbuk National University. Today, I will present our research on FPGA-based MLP Hardware Accelerator for Real-Time Destination Prediction in Autonomous Vehicles.
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| ICACT20260254 Slide.02
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Here is the outline. I will cover Introduction, Related Work, Proposed Method, Implementation, Results, and Conclusion.
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| ICACT20260254 Slide.03
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As autonomous vehicle technology advances, there is a growing need for intelligent destination prediction services. Personalized services reflecting individual preferences are emerging as key technologies.
The system must predict destinations based on historical data and contextual information. Most importantly, real time responsiveness is essential for practical AI services in automotive environments.
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| ICACT20260254 Slide.04
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Software-based neural network inference on embedded processors creates significant performance bottlenecks and fails to meet real time requirements.
LSTM models have been widely used for destination prediction, but they have clear limitations for hardware implementation. Complex gate structures, recurrent data dependencies, and high memory bandwidth requirements make FPGA implementation inefficient.
Therefore, we need hardware-friendly lightweight models for low-latency AI inference within vehicles.
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| ICACT20260254 Slide.05
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Our research objective is to propose an MLP based hardware accelerator replacing complex LSTM models for real-time destination prediction.
The system takes 7 input features and predicts 6 destination classes. We compare performance between Processing System and Programmable Logic on the Zynq 7000 platform. The expected benefits include significant performance improvement and low latency inference.
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| ICACT20260254 Slide.06
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Previous studies by Choi et al. and Jeong et al. used LSTM based approaches for destination prediction with high accuracy.
However, these studies focused only on software implementation and did not consider hardware deployment. This highlights the need for approaches designed with hardware efficiency in mind.
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| ICACT20260254 Slide.07
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Several studies explored LSTM acceleration on FPGA, including Han et al.s ESE and Zhang et al.s pipeline optimization work.
However, LSTM has fundamental hardware limitations. The 3 gate architecture requires complex control logic, and sequential dependencies limit parallelization.
In contrast, MLPs feed forward structure enables straightforward parallelization, achieving higher throughput and lower latency with fewer hardware resources.
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| ICACT20260254 Slide.08
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This figure shows our overall system architecture with three components: OBU for data collection, Private Server for model training, and ZYNQ platform for inference acceleration.
During inference, data flows directly from OBU to ZYNQ, bypassing the server for low-latency prediction.
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| ICACT20260254 Slide.09
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We employ a three-tier architecture separating data collection, model training, and inference acceleration.
The OBU handles in vehicle data collection. The Private Server performs MLP model training while maintaining data privacy. The ZYNQ Platform serves as a dedicated inference engine for real-time prediction.
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| ICACT20260254 Slide.10
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The OBU collects sensor and contextual information including device ID, location coordinates, and temporal data.
The Private Server receives training data, stores it securely, and performs MLP model training locally rather than relying on external cloud services.
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| ICACT20260254 Slide.11
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The ZYNQ Platform processes current context data to generate immediate prediction results. No network communication is required during inference, enabling submillisecond response time through hardware acceleration.
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| ICACT20260254 Slide.12
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This figure shows our MLP Network Architecture. It is a 4 layer feed forward structure with 7 input features, hidden layers of 64, 32, and 16 neurons with ReLU activation, and 6 output classes with Softmax.
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| ICACT20260254 Slide.13
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The network is optimized for FPGA implementation, balancing prediction accuracy with hardware constraints.
The pyramidal structure progressively extracts higher level features while reducing computational complexity. ReLU activation maintains computational efficiency, and Softmax produces probability distributions for 6 destinations.
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| ICACT20260254 Slide.14
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The 7 input features are categorized into three types. Device Info for user identification, Spatial information for current location, and Temporal information for time patterns. These answer who, where, and when for destination prediction.
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| ICACT20260254 Slide.15
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The model predicts 6 destination classes: Home1, Home2, CBNU, Hospital, Gym, and Yeongoong.
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| ICACT20260254 Slide.16
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We implemented our system on the Zynq-7000 SoC using ZedBoard. The Processing System has a dual core ARM Cortex A9 for system control. The Programmable Logic hosts our MLP hardware accelerator.
We used Vitis HLS 2022.2 for high level synthesis and Vivado 2022.2 for implementation. AXI Stream Interface ensures efficient data transfer between PS and PL.
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| ICACT20260254 Slide.17
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The Zynq SoC combines ARM processor with FPGA fabric, enabling software flexibility and hardware acceleration. The PS handles preprocessing while the PL performs parallel computation through pipelined architecture with minimal latency data exchange.
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| ICACT20260254 Slide.18
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This figure shows our inference results. The FPGA accelerator successfully predicts Home1 with 99.1 percent confidence. The clear probability distribution demonstrates reliable destination classification based on contextual input features.
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| ICACT20260254 Slide.19
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Here are the key performance results measured over 1000 runs. The PS Software Inference Time was 0.374 milliseconds. The PL Hardware Inference Time was only 0.005 milliseconds.
This represents a 68.53 times speedup through FPGA hardware acceleration. We achieved sub millisecond response time, meeting real time requirements for autonomous vehicle applications.
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| ICACT20260254 Slide.20
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In conclusion, we proposed an MLP based FPGA hardware accelerator for real time destination prediction. Our 4 layer architecture reduces complexity compared to LSTM while achieving 68.53 times speedup and sub millisecond response time. This demonstrates the viability of Edge AI inference in automotive embedded environments.
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| ICACT20260254 Slide.21
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For future work, we plan to expand features with traffic and weather data, investigate multi vehicle collaborative learning, and pursue advanced FPGA optimization including quantization and pruning techniques.
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| ICACT20260254 Slide.22
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Please refer to the slides for the complete list of references used in this research.
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| ICACT20260254 Slide.23
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Please refer to the slides for the complete list of references used in this research.
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| ICACT20260254 Slide.24
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This concludes my presentation. Thank you for your attention. For any questions, please contact me at qga0809@chungbuk.ac.kr. Thank you.
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