 ICACT20260323 Slide.01
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Hello, I’m Shuangyan Wang from the Intelligent Networking and Information Processing Lab, Institute of Acoustics, CAS. This talk presents HPPC, a DDR-optimized packet caching architecture for hop-local loss recovery on high-speed, long-RTT WAN segments. HPPC places a memory-rich in-path node that buffers recent packets in a unified DDR ring and uses a compact two-level flow-aware index for O(1) lookup. When the downstream node detects sequence gaps, it issues NACKs and the upstream node performs fast readback and retransmission within one segment RTT, without requiring changes to TCP/RDMA endpoints. |
| ICACT20260323 Slide.02
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On high-speed WANs, bandwidth is high but RTT is also large, so the bandwidth–delay product becomes huge. For reliable transports, each loss event triggers feedback and retransmission, and the recovery latency is fundamentally bounded by the control-loop RTT. Even modest random loss can therefore reduce goodput far below line rate. Our goal is to shorten the recovery loop: instead of paying the end-to-end RTT, we repair losses within one WAN segment RTT using hop-local mechanisms. |
| ICACT20260323 Slide.03
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Pure end-to-end recovery is inherently limited by the full RTT, which becomes costly on WANs. Even NIC-based selective retransmission still pays full-path feedback delay, and it requires significant per-flow state that must fit into limited on-chip SRAM. As the number of flows and the effective window size grow with BDP, SRAM becomes the scaling bottleneck. This motivates an in-path approach that can leverage larger off-chip memory while keeping the critical operations fast. |
| ICACT20260323 Slide.04
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Hop-local recovery cannot work without buffering, because the upstream node must retransmit previously sent packets upon receiving NACKs. This implies a sliding-window cache of recent packets at the upstream node. The challenge is that DDR provides capacity but is inefficient for fine-grained random access. Naive per-flow buffers or linked structures introduce pointer chasing and scattered DDR reads, resulting in poor row-buffer locality and high read amplification. We therefore need a DDR-friendly cache organization. |
| ICACT20260323 Slide.05
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This slide shows the deployment model of HPPC. We place two HPPC-capable in-path nodes that define a reliability segment. The upstream node forwards packets as usual and simultaneously clones them into a unified DDR ring while updating a compact index. The downstream node monitors sequence continuity per flow and sends NACKs, potentially as ranges, when it detects gaps. Upon receiving a NACK, the upstream node performs O(1) lookup, reads back the missing packets using aligned DDR bursts, and retransmits them within one segment RTT. Importantly, endpoints and TCP/RDMA remain unchanged. |
| ICACT20260323 Slide.06
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This slide explains how HPPC performs hop-local loss recovery within a single protected segment.
On the left, we summarize the process into four stages, all of which complete within one segment RTT, denoted as 𝑇seg.
First, the upstream HPPC clones packets into the DDR ring.
When a packet arrives at the upstream HPPC node, it is forwarded as usual, while its payload is simultaneously cloned into a DDR-resident circular buffer.
Importantly, this is done using sequential burst writes to preserve DDR row-buffer locality and minimize access overhead.
Second, the downstream HPPC detects a sequence gap.
At the other end of the protected segment, the downstream HPPC checks packet sequence continuity on a per-flow basis.
If a later packet arrives while an earlier sequence number is missing, a gap is detected locally.
Third, a NACK is generated and propagated back.
Upon detecting the gap, the downstream HPPC generates a NACK, typically covering a range of missing packets rather than a single sequence number.
This NACK travels back to the upstream node along the reverse control path, with a propagation delay of approximately half a segment RTT, or Tseg/2.
Finally, the upstream HPPC performs burst read and retransmission.
Once the NACK is received, the upstream HPPC uses its compact index to locate the corresponding packets in the DDR ring,
reads them out sequentially in bursts, and retransmits the missing packets in a range-coalesced manner.
Overall, this timeline shows that HPPC can detect and repair losses entirely within one segment RTT,
avoiding slow end-to-end congestion control reactions and enabling high goodput over long-BDP wide-area networks. |
| ICACT20260323 Slide.07
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Here we summarize the design targets and the key constraints. We want line-rate caching and loss repair at 100 Gb/s, fast enough to fetch missing packets quickly after NACKs arrive, and scalable to thousands of concurrent flows under large BDP and non-zero loss. The constraints are mainly memory-related: on-chip SRAM cannot store a full per-packet index for multi-GB DDR, while DDR provides capacity but performs poorly under fine-grained random accesses. Therefore, the cache must avoid per-flow linked structures and align operations with DDR’s burst-friendly behavior. |
| ICACT20260323 Slide.08
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In one sentence, HPPC is a DDR-resident packet cache that converts caching into predominantly sequential DDR bursts using a unified ring plus a compact two-level index. Our contributions are: a flow-agnostic DDR ring for sequential writes without per-flow allocation; a two-level flow-aware index enabling O(1) mapping from (flow, seq) to ring location with small SRAM footprint; range-aware repair that coalesces NACKs into long burst readbacks to keep read amplification low; and a dual-DDR4 FPGA prototype validated at 100 Gb/s with strong goodput under loss and 1,000+ flows. |
| ICACT20260323 Slide.09
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This slide provides the cache overview. HPPC stores all packet payloads in a unified ring buffer in DDR_data, using a fixed slot size aligned to burst transfers, which makes the write path naturally sequential. Metadata is placed in a separate DDR_idx channel, implementing a two-level index: L1 keeps per-flow window and pointers, and L2 stores fixed-size segments of address entries. On-chip SRAM only caches a small set of hot L1 entries and control FIFOs. The result is a sequential data path with bounded O(1) index operations and elastic cache sharing across flows under a global cap. |
| ICACT20260323 Slide.10
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The write path is designed to be sequential. Each packet is forwarded normally, while a clone of its payload is written into the DDR_data ring using burst-aligned transfers. In parallel, we append an address entry into DDR_idx, recording the ring offset, packet length, and epoch bits for validity checking. A single global write pointer eliminates per-flow fragmentation and allocator overhead. The ring operates with cyclic overwrite, deterministically overwriting the oldest data. |
| ICACT20260323 Slide.11
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The ring must be large enough to retain packets across the entire repair pipeline: cloning, loss detection, NACK return, readback, and retransmission. A simple guideline is to cover at least one segment BDP, R⋅Tseg, multiplied by a safety factor α≥1 to account for burst losses, control jitter, and overlap margin. In practice, the ring is provisioned in fixed slots, with slot size aligned to DDR burst width, so both writes and readbacks remain efficient. |
| ICACT20260323 Slide.12
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The two-level index enables O(1) lookup even when most metadata resides in DDR. L1 is a per-flow directory that stores the window bounds and pointers to the L2 chain, and hot entries are cached in on-chip SRAM. L2 consists of fixed-size segments in DDR_idx, each containing K address entries. Given (flow, seq), we compute the offset Δ from the window start and use division/modulo to locate the segment and the entry. Epoch bits provide a lightweight validity check to prevent stale references after overwrite or eviction. |
| ICACT20260323 Slide.13
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To enable elastic sharing across flows, HPPC manages L2 segments as a global pool with a cap Mmax. We maintain a free FIFO for available segments and an oldest-full FIFO that tracks segments in the order they become full. When a flow needs a new segment, we allocate from the free FIFO; if empty, we evict the globally oldest full segment and reassign it. This avoids per-flow reclamation complexity, mitigates fragmentation, and lets cache capacity follow recent traffic intensity rather than fixed per-flow quotas. |
| ICACT20260323 Slide.14
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Repair efficiency depends strongly on NACK granularity. If the downstream sends a NACK per missing packet, the upstream may perform many small lookups and fragmented DDR reads. HPPC supports range NACKs, where a contiguous missing sequence interval is represented as one message. The upstream then performs bounded O(1) index lookups and coalesces adjacent address entries into long read windows, enabling aligned burst readbacks and improving both control overhead and DDR efficiency. |
| ICACT20260323 Slide.15
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Read amplification captures how much DDR traffic is required to retransmit a given amount of data. Chain-based caches tend to chase pointers and issue scattered reads, resulting in high amplification and poor DDR efficiency. HPPC combines a unified ring layout with range-aware NACK coalescing to produce long contiguous read windows, so the bytes read from DDR closely match the bytes retransmitted, driving RAdata toward 1. This leaves more DDR bandwidth headroom for cloning and reduces latency variability. |
| ICACT20260323 Slide.16
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We implement HPPC on an FPGA-based NIC prototype with two independent DDR4 channels. DDR_data is dedicated to the payload ring buffer, while DDR_idx stores the index metadata, including the L1/L2 structures and the global queues. This separation reduces contention between large sequential payload bursts and smaller metadata accesses. The datapath is fully pipelined, covering parsing, cloning into the ring, NACK handling, index lookup, readback scheduling, and retransmission, with rate limiting and backpressure to protect normal forwarding. |
| ICACT20260323 Slide.17
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Our testbed consists of two HPPC-capable prototype nodes forming a reliability segment. Traffic is generated and measured using an IXIA AresONE system operating in 100 GbE mode. A WAN emulator injects controlled random loss and enforces a fixed RTT to emulate WAN-like conditions. We measure wire-level throughput and goodput and verify residual loss at the receiver. Other factors such as firmware, clocking, and offloads are kept constant to ensure the observed trends are driven by loss and the cache/repair behavior. |
| ICACT20260323 Slide.18
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Our testbed consists of two HPPC-capable prototype nodes forming a reliability segment. Traffic is generated and measured using an IXIA AresONE system operating in 100 GbE mode. A WAN emulator injects controlled random loss and enforces a fixed RTT to emulate WAN-like conditions. We measure wire-level throughput and goodput and verify residual loss at the receiver. Other factors such as firmware, clocking, and offloads are kept constant to ensure the observed trends are driven by loss and the cache/repair behavior. |
| ICACT20260323 Slide.19
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We compare HPPC against a chain-based cache that maintains per-flow linked buffers in DDR, which induces pointer chasing and scattered accesses. We also discuss a single-level flat index as an analytical strawman: storing per-packet indices in fast memory is capacity-limited, while placing the index in DDR increases the number of DDR transactions on the critical path. We additionally include qualitative reference markers from P4-based loss masking and NIC-based selective retransmission, but our main focus is structural: how ring-plus-two-level indexing improves DDR access patterns and efficiency at line rate. |
| ICACT20260323 Slide.20
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This slide reports HPPC goodput under random loss on a WAN-like 100-Gb/s segment. The prototype is implemented on the MA-X1 platform with an XCVU9P FPGA and dual DDR4 channels. Traffic is generated by an IXIA XM100GE4CXP tester, and a WAN emulator fixes the RTT to 100 ms. We sweep packet sizes from 256 to 4096 bytes and random loss rates up to 5%.
The key result is that HPPC sustains near line-rate goodput for packet sizes of 1500 bytes and above up to 0.1% loss. Even at 1% loss, goodput stays above 95 Gb/s for 2048B and 4096B packets, and around 95 Gb/s for 1500B. The normalized curves for ≥1500B largely overlap, indicating that performance is dominated by the fraction of DDR readback bandwidth consumed by repairs, rather than increasing lookup cost—consistent with sequential ring accesses and range-coalesced burst readback.
For smaller packets (≤1024B), throughput plateaus due to the FPGA packet-rate processing limit, not due to cache inefficiency or DDR contention. |
| ICACT20260323 Slide.21
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We acknowledge several limitations. Our experiments use synthetic CBR traffic and independent random loss; real WAN traces may involve correlated losses, burstiness, flow churn, and mixed packet sizes, which could stress NACK coalescing and segment pool management differently. We evaluate a single HPPC segment and do not explore multi-hop deployments or interactions across segments. Comparisons to P4 and SR-NIC designs rely on published results as qualitative references rather than head-to-head tests on identical hardware. Nevertheless, the evaluation demonstrates the structural advantage of the ring-plus-two-level index design in achieving DDR-friendly sequential access at line rate. |
| ICACT20260323 Slide.22
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To conclude, fast loss recovery on WANs fundamentally requires a line-rate sliding-window cache. DDR provides the necessary capacity, but only if the cache is organized to be burst-friendly. HPPC achieves this with a unified ring buffer and a compact two-level index, turning most operations into sequential DDR accesses. Our FPGA prototype demonstrates strong goodput under non-zero loss on a 100 GbE segment. Future work includes evaluation with real WAN traces, multi-segment deployments, and exploring SmartNIC/ASIC implementations and tighter integration with congestion control. Thank you, and I’m happy to take questions. |
| ICACT20260323 Slide.23
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Finally, acknowledgments and references. We cite WAN deployment experience papers (e.g., B4 and related works), classic TCP performance modeling for high-BDP networks, and RDMA/congestion control literature. We acknowledge support from the SEANet wide-area RDMA transport acceleration project, with the grant number listed on the slide. |
| ICACT20260323 Slide.24
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Thank you for your listening! |
